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Frontiers of Computer Science

ISSN 2095-2228

ISSN 2095-2236(Online)

CN 10-1014/TP

邮发代号 80-970

2019 Impact Factor: 1.275

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Frontiers of Computer Science  2024, Vol. 18 Issue (6): 186908   https://doi.org/10.1007/s11704-023-2492-3
  本期目录
A new design of parity-preserving reversible multipliers based on multiple-control toffoli synthesis targeting emerging quantum circuits
Mojtaba NOORALLAHZADEH1(), Mohammad MOSLEH1(), Kamalika DATTA2,3
1. Department of Computer Engineering, Dezful Branch, Islamic Azad University, Dezful, Iran
2. German Research Centre for Artificial Intelligence (DFKI), Bremen 28359, Germany
3. Institute of Computer Science, University of Bremen, Bremen 28359, Germany
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Abstract：

With the recent demonstration of quantum computers, interests in the field of reversible logic synthesis and optimization have taken a different turn. As every quantum operation is inherently reversible, there is an immense motivation for exploring reversible circuit design and optimization. When it comes to faults in circuits, the parity-preserving feature donates to the detection of permanent and temporary faults. In the context of reversible circuits, the parity-preserving property ensures that the input and output parities are equal. In this paper we suggest six parity-preserving reversible blocks (Z, F, A, T, S, and L) with improved quantum cost. The reversible blocks are synthesized using an existing synthesis method that generates a netlist of multiple-control Toffoli (MCT) gates. Various optimization rules are applied at the reversible circuit level, followed by transformation into a netlist of elementary quantum gates from the NCV library. The designs of full-adder and unsigned and signed multipliers are proposed using the functional blocks that possess parity-preserving properties. The proposed designs are compared with state-of-the-art methods and found to be better in terms of cost of realization. Average savings of 25.04%, 20.89%, 21.17%, and 51.03%, and 18.59%, 13.82%, 13.82%, and 27.65% respectively, are observed for 4-bit unsigned and 5-bit signed multipliers in terms of quantum cost, garbage output, constant input, and gate count as compared to recent works.
Key words： reversible circuits    parity-preserving    NCV library    multiple-control Toffoli gates    quantum circuits    quantum cost
收稿日期: 2022-07-30      出版日期: 2023-09-26
Corresponding Author(s): Mojtaba NOORALLAHZADEH,Mohammad MOSLEH   
 引用本文:   
. [J]. Frontiers of Computer Science, 2024, 18(6): 186908.
Mojtaba NOORALLAHZADEH, Mohammad MOSLEH, Kamalika DATTA. A new design of parity-preserving reversible multipliers based on multiple-control toffoli synthesis targeting emerging quantum circuits. Front. Comput. Sci., 2024, 18(6): 186908.
 链接本文:  
https://academic.hep.com.cn/fcs/CN/10.1007/s11704-023-2492-3
https://academic.hep.com.cn/fcs/CN/Y2024/V18/I6/186908
Fig.1  
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Fig.3  
Fig.4  
Fig.5  
Fig.6  
Fig.7  
Fig.8  
Fig.9  
Fig.10  
Fig.11  
Fig.12  
Fig.13  
Fig.14  
Size of multiplier Performance metrics
QC GO CI GC
4×4 151 39 39 19
8×8 679 171 171 109
12×12 1591 399 399 263
16×16 2887 723 723 481
32×32 11911 2979 2979 1993
Tab.1  
Fig.15  
Fig.16  
Fig.17  
Size of multiplier Performance metrics
QC GO CI GC
5×5 262 74 74 35
8×8 706 191 191 92
12×12 1634 431 431 210
16×16 2946 767 767 376
32×32 12034 3071 3071 3040
Tab.2  
Designs QC GO CI GC Improv. (in QC)/%
[10] 20 3 2 4 65.00
[11] 18 6 5 6 61.11
[12] 14 3 2 2 50.00
[13] 14 3 2 1 50.00
[14] 14 3 2 2 50.00
[15] 14 3 2 2 50.00
[16] 11 3 2 4 36.36
[17] 11 3 2 1 36.36
[18] 10 3 2 3 30.00
[19] 10 3 2 1 30.00
[20] 10 3 2 3 30.00
[21] 8 3 2 1 12.50
[22] 8 3 2 1 12.50
[23] 8 3 2 1 12.50
Proposed 7 3 2 1 –
Average (in QC) 37.59
Tab.3  
Module Design QC GO CI GC
PPG [25] 104 32 40 28
[24] 89 17 25 16
[26] 96 24 32 24
[23] 89 17 23 16
Proposed 83 13 19 9
% improv. [25] 20.19 59.37 52.50 67.85
% improv.[24] 6.74 23.52 24.00 43.75
% improv.[26] 13.54 45.83 40.62 62.50
% improv.[23] 6.74 23.52 17.39 43.75
Average 11.80 38.06 33.62 54.46
MOA [25] 140 32 24 20
[24] 116 32 24 36
[26] 88 32 24 12
[23] 80 28 22 10
Proposed 68 26 20 10
% improv. [25] 51.42 18.75 16.66 50.00
% improv.[24] 41.37 18.75 16.66 72.22
% improv.[26] 22.72 18.75 16.66 16.66
% improv.[23] 15.00 7.14 9.09 0.00
Average 32.62 15.84 14.76 34.72
Tab.4  
Designs QC GO GI GC
[25] 244 64 64 48
[24] 205 49 49 52
[26] #1 184 56 56 36
[26] #2 177 49 49 28
[27] 184 44 44 33
[23] 169 45 45 26
[28] 300 44 45 124
Proposed 151 39 39 19
% improv. [25] 38.11 39.06 39.06 60.41
% improv. [24] 26.34 20.40 20.40 63.46
% improv. [26] #1 17.93 30.35 30.35 47.22
% improv. [26] #2 14.68 20.40 20.40 32.14
% improv. [27] 17.93 11.36 11.36 42.42
% improv. [23] 10.65 13.33 13.33 26.92
% improv. [28] 49.66 11.36 13.33 84.67
Average 25.04 20.89 21.17 51.03
Tab.5  
Module Design QC GO CI GC
PPG [12] 149 34 49 37
[26] 143 28 43 25
[23] 143 28 41 25
Proposed 136 22 35 16
% improve.[12] 8.72 35.29 28.57 56.75
% improve.[26] 4.89 21.42 18.60 36.00
% improve.[23] 4.89 21.42 14.63 36.00
Average 6.16 26.04 20.6 42.91
MOA [12] 252 55 41 20
[26] 154 58 43 21
[23] 146 54 41 19
Proposed 126 52 39 19
% improve.[12] 50.00 5.45 4.87 5.00
% improve.[26] 18.18 10.34 9.30 9.52
% improve.[23] 13.69 3.70 4.87 0.00
Average 27.29 6.49 6.34 4.84
Tab.6  
Designs QC GO GI GC
[12] 401 90 90 57
[26] 297 86 86 46
[23] 289 82 82 44
Proposed 262 74 74 35
% improv. [12] 34.66 17.77 17.77 38.59
% improv. [26] 11.78 13.95 13.95 23.91
% improv. [23] 9.34 9.75 9.75 20.45
Average 18.59 13.82 13.82 27.65
Tab.7  
Fig.18  
  
  
  
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