An effective fault localization approach for Verilog based on enhanced contexts

doi:10.1007/s11704-024-2622-6

Front. Comput. Sci.

2024, Vol. 18

Issue (5) : 185108 https://doi.org/10.1007/s11704-024-2622-6

Architecture

An effective fault localization approach for Verilog based on enhanced contexts

Zhuo ZHANG¹, Ya LI², Lei XIA³(

), Jianxin XUE⁴, Jiang WU⁵, Xiaoguang MAO⁵

¹. School of Computer Science and Engineering, Xi’an University of Technology, Xi’an 710048, China
². Ningbo Artificial Intelligence Institute, Shanghai Jiao Tong University, Ningbo 315000, China
³. No.83 Army Joint and Truma Disease Treatment Centre of PLA, Xinxiang 453000, China
⁴. Department of Software Engineering, Shanghai Second Polytechnic University, Shanghai 201209, China
⁵. College of Computer, National University of Defense Technology, Changsha 410073, China

Download: PDF(2527 KB) HTML
Export: BibTeX | EndNote | Reference Manager | ProCite | RefWorks

Corresponding Author(s): Lei XIA

Just Accepted Date: 29 March 2024 Issue Date: 13 May 2024

Cite this article:

Zhuo ZHANG,Ya LI,Lei XIA, et al. An effective fault localization approach for Verilog based on enhanced contexts[J]. Front. Comput. Sci., 2024, 18(5): 185108.

URL:

https://academic.hep.com.cn/fcs/EN/10.1007/s11704-024-2622-6
https://academic.hep.com.cn/fcs/EN/Y2024/V18/I5/185108

Name	Formula
Russel_Rao	$α e f α e f + α n f + α e p + α n p$
Dstar	$α e f ∗ α n f + α e p$
OPTIMAL_P	$α e f ? α e p α e p + α n p + 1$
Ochiai	$α e f α e f + α n f + α e f + α e p$
GP02	$2 (α e f + α n p) + α e p$
GP03	$\| α e f 2 ? α e p \|$
GP19	$α e f \| α e p ? α e f + α n f ? α n p \|$

Tab.1 Definitions of evaluation metrics used

Tab.2 Test suite information

Fig.1 RImp comparison of ContextHD over fault localization approaches

1	P, Flake P, Moorby S, Golson A, Salz S Davidmann . Verilog HDL and its ancestors and descendants. Proceedings of the ACM on Programming Languages, 2020, 4( HOPL): 87
2	H D Foster . Trends in functional verification: a 2014 industry study. In: Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference. 2015, 1−6
3	I, Kuon J Rose . Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26( 2): 203–215
4	H Foster . The 2020 Wilson research group functional verification study. See Blogs.sw.siemens.com/verificationhorizons/2020/11/10/part-2-the-2020-wilson-research-group-functional-verification-study website, 2020
5	G, Agha K Palmskog . A survey of statistical model checking. ACM Transactions on Modeling and Computer Simulation, 2018, 28( 1): 6
6	S Y, Huang K T, Cheng K C, Chen J Y J Lu . Fault-simulation based design error diagnosis for sequential circuits. In: Proceedings of 1998 Design and Automation Conference. 1998, 632−637
7	A, Mahzoon D, Große R Drechsler . Combining symbolic computer algebra and Boolean satisfiability for automatic debugging and fixing of complex multipliers. In: Proceedings of 2018 IEEE Computer Society Annual Symposium on VLSI. 2018, 351−356
8	W E, Wong R, Gao Y, Li R, Abreu F Wotawa . A survey on software fault localization. IEEE Transactions on Software Engineering, 2016, 42( 8): 707–740
9	T Y, Jiang C N J, Liu J Y Jou . Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. In: Proceedings of 2005 IEEE International Symposium on Circuits and Systems. 2005, 5682−5685

[1]

FCS-22622-OF-ZZ_suppl_1

Download

Viewed

Full text

Abstract

Cited

Shared

Discussed