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Parallel VLSI design for the fast 3-D DWT core algorithm |
| WEI Benjie1, LIU Mingye2, ZHOU Yihua2, CHENG Baodong2 |
| 1.School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China; The Department of Computer Science, Beijing Electronic Science and Technology Institute, Beijing 100070, China; 2.School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China; |
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Abstract By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth, this paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs). Based on the implementation of a 3-D DWT software, a parallel architecture design of a very large-scale integration (VLSI) is produced. It needs three dual-port random-access memory (RAM) to store the temporary results and transpose the matrix, then builds up a pipeline model composed of the three 1-D DWTs. In the design, the finite state machine (FSM) is used well to control the flow. Compared with the serial mode, the experimental results of the post synthesized simulation show that the design method is correct and effective. It can increase the processing speed by about 66%, work at 59 MHz, and meet the real-time needs of the video encoder.
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Issue Date: 05 March 2007
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