Analytical delay models for RLC interconnects under ramp input

doi:10.1007/s11460-007-0016-9

Front. Electr. Electron. Eng.

2007, Vol. 2

Issue (1) : 88-91 https://doi.org/10.1007/s11460-007-0016-9

Analytical delay models for RLC interconnects under ramp input

REN Yinglei, MAO Junfa, LI Xiaochun

Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai 200030, China;

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Abstract Analytical delay models for Resistance Inductance Capacitance (RLC) interconnects with ramp input are presented for different situations, which include overdamped, underdamped and critical response cases. The errors of delay estimation using the analytical models proposed in this paper are less by 3% in comparison to the SPICE-computed delay. These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input.

Issue Date: 05 March 2007

Cite this article:

MAO Junfa,REN Yinglei,LI Xiaochun. Analytical delay models for RLC interconnects under ramp input[J]. Front. Electr. Electron. Eng., 2007, 2(1): 88-91.

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https://academic.hep.com.cn/fee/EN/10.1007/s11460-007-0016-9
https://academic.hep.com.cn/fee/EN/Y2007/V2/I1/88

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