Frontiers of Electrical and Electronic Engineering

ISSN 2095-2732

ISSN 2095-2740(Online)

CN 10-1028/TM

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Co-regulated gene module detection for time series gene expression data
Wanwan TANG, Rui LI, Shao LI, Yanda LI
Front Elect Electr Eng    2012, 7 (4): 357-366.   https://doi.org/10.1007/s11460-012-0207-x
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It is important to detect interaction effect of multiple genes during certain biological process. In this paper, we proposed, from systems biology perspective, the concept of co-regulated gene module, which consists of genes that are regulated by the same regulator(s). Given a time series gene expression data, a hidden Markov model-based Bayesian model was developed to calculate the likelihood of the observed data, assuming the co-regulated gene modules are known. We further developed a Gibbs sampling strategy that is integrated with reversible jump Markov chain Monte Carlo to obtain the posterior probabilities of the co-regulated gene modules. Simulation study validated the proposed method. When compared with two existing methods, the proposed approach significantly outperformed the conventional methods.

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Iterative hybrid decoding algorithm for LDPC codes based on attenuation factor
Minghua LIU, Lijun ZHANG
Front Elect Electr Eng    0, (): 279-285.   https://doi.org/10.1007/s11460-012-0195-x
Abstract   HTML   PDF (160KB)

An attenuated iterative reliability-based majority-logic (AIML) decoding algorithm for low-density parity-check (LDPC) codes is proposed, which pertains to hybrid decoding schemes. The algorithm is devised based on the orthogonal check-sums of one-step majority-logic (OSMLG) decoding algorithm in conjunction with certain of reliability measures of the received symbols. Computation of reliability measure of the syndrome sum is refined by introducing an attenuation factor. Simulation results show that, in binary-input additive white Gaussian noise (BI-AWGN) channel, the AIML decoding algorithm outperforms other popular iterative reliability-based majority-logic (IML) decoding algorithms with a slight increase in computational complexity. Within maximum iteration number of 5, the AIML algorithm can achieve almost identical error performance to sum-product algorithm (SPA). No error floor effect can be observed for the AIML algorithm down to the bit error rate (BER) of 10-8, while error floor appears for SPA around the BER of 10-7 even with maximum iteration number of 100. Furthermore, the inherent feature of parallel procession for AIML algorithm enforces the decoding speed in contrast to those serial decoding schemes, such as weighted bit-flipping (WBF) algorithm.

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Machine learning and intelligence science: IScIDE (C)
Lei XU, Yanda LI
Front Elect Electr Eng    2012, 7 (1): 1-4.   https://doi.org/10.1007/s11460-012-0194-y
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