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Frontiers of Optoelectronics

ISSN 2095-2759

ISSN 2095-2767(Online)

CN 10-1029/TN

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Front Optoelec Chin    2011, Vol. 4 Issue (2) : 146-149    https://doi.org/10.1007/s12200-011-0156-7
RESEARCH ARTICLE
Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods
Guangli WANG, Yi SHI(), Lijia PAN(), Lin PU, Jin LV, Rong ZHANG, Youdou ZHENG
School of Electronic Science and Technology, Key Laboratory of Photonic and Electronic Materials, Nanjing University, Nanjing 210093, China
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Abstract

The Ge/Si nanocrystals on ultra thin high-k tunnel oxide Al2O3 were fabricated to form the charge trapping memory prototype with asymmetric tunnel barriers through combining the advanced atomic layer deposition (ALD) and pulse laser deposition (PLD) techniques. Charge storage characteristics in such memory structure have been investigated using capacitance-voltage (C-V) and capacitance-time (C-t) measurements. The results prove that both the two-layered and three-layered memory structures behave relatively qualified for the multi-level cell storage. The results also demonstrate that compared to electrons, holes reach a longer retention time even with an ultra thin tunnel oxide owing to the high band offset at the valence band between Ge and Si.
Keywords high-k tunnel oxide      equivalent oxide thickness (EOT)      charge trapping memory (CTM) prototype      atomic layer deposition (ALD) technique      multi-level cell (MLC) storage     
Corresponding Author(s): SHI Yi,Email:yshi@nju.edu.cn; PAN Lijia,Email:ljpan@nju.edu.cn   
Issue Date: 05 June 2011
 Cite this article:   
Guangli WANG,Yi SHI,Lijia PAN, et al. Charge trapping memory devices employing multi-layered Ge/Si nanocrystals for storage fabricated with ALD and PLD methods[J]. Front Optoelec Chin, 2011, 4(2): 146-149.
 URL:  
https://academic.hep.com.cn/foe/EN/10.1007/s12200-011-0156-7
https://academic.hep.com.cn/foe/EN/Y2011/V4/I2/146
Fig.1  Schematic diagram of bi-layered Si/Ge NCs based CTM
Fig.1  Schematic diagram of bi-layered Si/Ge NCs based CTM
Fig.2  TEM image of bi-layered Si/Ge NCs based CTM
Fig.2  TEM image of bi-layered Si/Ge NCs based CTM
Fig.3  - hysteresis loops of bi-layered Si/Ge NCs based CTM
Fig.3  - hysteresis loops of bi-layered Si/Ge NCs based CTM
Fig.4  (a) shift versus of bi-layered Si/Ge NCs based CTM; (b) shift versus of tri-layered Si/Ge NCs based CTM
Fig.4  (a) shift versus of bi-layered Si/Ge NCs based CTM; (b) shift versus of tri-layered Si/Ge NCs based CTM
Fig.5  - curve of bi-layered Si/Ge NCs based CTM
Fig.5  - curve of bi-layered Si/Ge NCs based CTM
Fig.6  Energy band diagram of bi-layered Si/Ge NCs based CTM
Fig.6  Energy band diagram of bi-layered Si/Ge NCs based CTM
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