Please wait a minute...
Shopping Cart Email List Chinese
Advanced Search Fig/Tab
Frontiers of Optoelectronics

ISSN 2095-2759

ISSN 2095-2767(Online)

CN 10-1029/TN

Postal Subscription Code 80-976

Featured Articles  |  Most Downloaded  |  Most Reading
Online Submission Subscribe to Our RSS Content Feed
Front Optoelec    2012, Vol. 5 Issue (3) : 271-278    https://doi.org/10.1007/s12200-012-0234-5
RESEARCH ARTICLE
High-speed optical binary data pattern recognition for network security applications
Xuelin YANG(), Cen WU, Weisheng HU
State Key Laboratory of Advanced Optical Communication Systems and Networks, Shanghai Jiao Tong University, Shanghai 200240, China
 Download: PDF(781 KB)   HTML
 Export: BibTeX | EndNote | Reference Manager | ProCite | RefWorks
Abstract

All-optical high-speed binary data pattern recognition is one of the key technologies in network security applications. A serial pattern recognition scheme is presented, which can detect and locate a specified random target pattern within an input data sequence at high bit-rate. The logic operation principle is presented using logic equations. The logic AND/XNOR gates and a re-circulating loop at 10.65–42.6 Gbit/s are successfully demonstrated using three semiconductor optical amplifier (SOA) based gates. The experiments have successfully demonstrated the random pattern recognition up to 256-bits at 42.6 Gbit/s.
Keywords semiconductor optical amplifiers (SOAs)      all-optical logic      XOR gates      high-speed optical signal procession     
Corresponding Author(s): YANG Xuelin,Email:x.yang@sjtu.edu.cn   
Issue Date: 05 September 2012
 Cite this article:   
Xuelin YANG,Cen WU,Weisheng HU. High-speed optical binary data pattern recognition for network security applications[J]. Front Optoelec, 2012, 5(3): 271-278.
 URL:  
https://academic.hep.com.cn/foe/EN/10.1007/s12200-012-0234-5
https://academic.hep.com.cn/foe/EN/Y2012/V5/I3/271
Fig.1  Schematic of pattern recognition system
BoldItalic01234567
BoldItalicBoldItalicBoldItalicBoldItalicBoldItalic01011100
01BoldItalic01011100
BoldItalic0,BoldItalic11111111
BoldItalic0,BoldItalic01011100
10BoldItalic10100011
BoldItalic1,BoldItalic00101110
BoldItalic1,BoldItalic00100010
21BoldItalic01011100
BoldItalic2,BoldItalic00010001
BoldItalic2,BoldItalic00010000
31BoldItalic01011100
BoldItalic3,BoldItalic00001000
BoldItalic3,BoldItalic00001000
Tab.1  Evolution of output signal , for an example sequence , and target (1011)
Fig.2  Waveform evolution for the data in Table 1
Fig.3  Experimental setup (a) and output (b) of 42.6 Gbit/s XNOR gate for target pattern= 1 (upper frame, original) and pattern= 0 (lower frame, inverted)
Fig.4  Setup (a) and output (b) of the re-circulating loop at 42.6Gbit/s. The waveforms show the evolution of the input data sequence (the original data are on top trace)
Fig.5  Experimental setup of the complete pattern recognition system at 10.65-2.6 Gbit/s
Fig.6  (a) Recognition of an 8-bit target at 10.65 Gbit/s: 1011 0100; (b) recognition of an 8-bit target at 21.3 Gbit/s: 1100 1100. The target patterns are marked by boxes in the original data. The waveforms show the evolution of the input data sequence. Each pulse in circulation No. 7 (Marked in a box) indicates the occurrence and location of the last bit of target pattern
XNOR gatedBm at 10 Gbit/sdBm at 20 Gbit/sdBm at 40 Gbit/s
clock, 10/20 GHz-13.32.06.5
push/pull-3.4/none1.6/-2.33.0
target CW-4.00.87.2
AND gate
data-12.5-7.0-8
push/pull-15.0-11.4/-21.6-6/-12
initializing pulse-9.5-9.5
regenerator
reset pulse9.59.512
push/pull1.0-2.4/-153/-5
Tab.2  Average input powers of XNOR gate, AND gate and regenerator at 10.65, 21.3 and 42.6 Gbit/s
Fig.7  Pattern recognition at 42.6 Gbit/s. (a) 8-bit target: 0000 0101; (b) 32-bit target: 1111 1111 0000 1010 1111 1010 1010 1101
Fig.8  Pattern recognition at 42.6 Gbit/s for target of (a) 64-bit; (b) 256-bit
1 Ramos F, Kehayas E, Martinez J M, Clavero R, Marti J, Stampoulidis L, Tsiokos D, Avramopoulos H, Zhang J, Holm-Nielsen P V, Chi N, Jeppesen P, Yan N, Monroy I T, Koonen A M J, Hill M T, Liu Y, Dorren H J S, Van Caenegem R, Colle D, Pickavet M, Riposati B. IST-LASAGNE: towards all-optical label swapping employing optical logic gates and optical flip-flops. Journal of Lightwave Technology , 2005, 23(10): 2993-3011
doi: 10.1109/JLT.2005.855714
2 Poustie A J, Blow K J, Kelly A E, Manning R J. All-optical parity checker. OFC/IOOC , 1999, 1: 137-139
3 Webb R P, Yang X L, Manning R J, Maxwell G D, Poustie A J, Lardenois S, Cotter D. 42Gbit/s all-optical pattern recognition system. OFC , 2008: OTuL2
4 Yang X L, Webb R P, Manning R J, Cotter D, Maxwell G D, Poustie A J, Lardenois S. Application of semiconductor optical amplifier logic gates in high-speed all-optical pattern recognition. ICTON , 2008, 148-151
5 Webb R P, Yang X, Manning R J, Giller R. All-optical 40 Gbit/s XOR gate with dual ultrafast nonlinear interferometer. Electronics Letters , 2005, 41(25): 1396-1397
doi: 10.1049/el:20052982
6 Poustie A J. Semiconductor devices for all-optical signal processing. ECOC , 2005, 3: 475-478
7 Webb R P, Yang X L, Manning R J, Maxwell G D, Poustie A J, Lardenois S, Cotter D. All-optical binary pattern recognition at 42 Gb/s. Journal of Lightwave Technology , 2009, 27(13): 2240-2245
doi: 10.1109/JLT.2008.2006067
8 Webb R P, Dailey J M, Manning R J, Maxwell G D, Poustie A J, Lardenois S, Harmon R, Harrison J, Kopidakis G, Athanasopoulos E, Krithinakis A, Doukhan F, Omar M, Vaillant D, Di Nallo F, Koyabe M, Di Cairano-Gilfedder C. All-optical header processing in a 42.6 Gb/s optoelectronic firewall. IEEE Journal of selected Topics in Quantum Electronics , 2012, 18(2): 757-764
Viewed
Full text


Abstract

Cited
  Shared   
  Discussed