Synthetic two-dimensional electronics for transistor scaling

doi:10.1007/s11467-023-1305-3

Front. Phys.

2023, Vol. 18

Issue (6) : 63601 https://doi.org/10.1007/s11467-023-1305-3

TOPICAL REVIEW

Synthetic two-dimensional electronics for transistor scaling

Zihan Wang, Yan Yang, Bin Hua, Qingqing Ji(

)

School of Physical Science and Technology, ShanghaiTech University, Shanghai 201210, China

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Abstract

Two-dimensional (2D) materials have been considered to hold promise for transistor ultrascaling, thanks to their atomically thin body immune to short-channel effects. The lower channel size limit of 2D transistors is yet to be revealed, as this size is below the spatial resolution of most lithographic techniques. In recent years, chemical approaches such as chemical vapor deposition (CVD) and metalorganic CVD (MOCVD) have been established to grow atomically precise nanostructures and heterostructures, thus allowing for synthetic construction of ultrascaled transistors. In this review, we summarize recent developments on the precise synthesis and defect engineering of electronic nanostructures/heterostructures aiming for transistor applications. We demonstrate with rich examples that ultrascaled 2D transistors are achievable by finely tuning the “growth-as-fabrication” process and could host a plethora of new device physics. Finally, by plotting the scaling trend of 2D transistors, we conclude that synthetic electronics possess superior scaling capability and could facilitate the development of post-Moore nanoelectronics.

Keywords 2D materials nanostructures synthetic electronics transistor scaling

Corresponding Author(s): Qingqing Ji

About author:

^* These authors contributed equally to this work.

Issue Date: 25 June 2023

Cite this article:

Zihan Wang,Yan Yang,Bin Hua, et al. Synthetic two-dimensional electronics for transistor scaling[J]. Front. Phys. , 2023, 18(6): 63601.

URL:

https://academic.hep.com.cn/fop/EN/10.1007/s11467-023-1305-3
https://academic.hep.com.cn/fop/EN/Y2023/V18/I6/63601

Fig.1 2D technology for transistor scaling. (a) Comparison of 2D transistors and FinFETs [36]. (b) Transistor scaling trend versus technology node and physical gate length [36]. (c) Schematic illustration of possible technologies in future chips incorporating 2D materials [36].

Fig.2 Ultrascaled 2D transistors enabled by nanofabrication. (a) TMD transistors with sub-10-nm channel length fabricated by corrosion crack of Bi₂O₃ [46]. (b) Schematic and transfer curve of a vertical transistor [56]. (c−e) A carbon nanotube-gated TMD transistor with (c) corresponding device structure, (d) transfer curve, and (e) output characteristics [50]. (f) Schematic of a graphene edge-gated transistor with (g) corresponding transfer characteristics [51].

Fig.3 Chemically derived GNRs. (a) Al ribbon-sheltered plasma etching of graphene for GNRs with width down to ~20 nm [58]. (b) PMMA-assisted plasma cutting of carbon nanotubes for GNRs [59]. (c) On-surface polymerization of organic monomers into GNRs [62]. (d) Step-induced CVD growth of GNRs [64].

Fig.4 Synthetic TMD nanoribbons. (a) Self-etching growth of MoTe₂ nanoribbon arrays and the AFM images [65]. (b) Step-guided growth of MoS₂ nanowires and the STM images [66]. (c) Growth of MoS₂ nanoribbons on (i) SiO₂/Si and (ii) phosphine-treated Si(001) substrates, together with (iii) the SEM image of MoS₂ nanoribbons [67]. (d) Growth of ultranarrow MoS₂ nanoribbons by Ni nanoparticle catalysis, with (i) showing the schematic of the growth process, and (ii, iii) the SEM images [71].

Fig.5 Synthetic TMD heterostructures. (a) Two-step growth of vertical VTe₂/WS₂ heterostructures [84]. (b) One-step growth of vertical NbS₂/MoS₂ heterostructures [85]. (c) Two-step growth of vertical VSe₂/WSe₂ heterostructures [86]. The second-layer growth initialized at (a) in-plane defects, (b) vertices, and (c) edges, respectively, of the first layers. (d) One-pot synthesis of lateral TMD heterostructures and multi-heterostructures [76]. (e) MoS₂/WS₂ heterobilayers with tunable stacking orders [87]. (f) Mosaic patterns of lateral TMD heterostructures [77]. (g) Vertical TMD superlattices fabricated by MOCVD [89]. (h) In-plane TMD superlattices grown by modulated MOCVD [90].

Fig.6 Defects in ultrascaled monolayer systems. (a) Random telegraph noise of currents induced by individual defects in ultrascaled MoS₂ FETs [93]. (b) Configurations of atomic dopants in TMDs [94]. (c) Zeeman shifts observed in V-doped WSe₂ by transport measurements [95]. (d) Bound hole states in monolayer V-doped WSe₂ by STS measurements [96]. (e) Edge effects of (i) graphene nanoribbons, with (ii) showing the dimensional difference of single-layer graphene (SLG) and SLRs, (iii) linear resistance−length (R−L) relation of SLG, (iv) and (v) exponential R−L relation of SLRs at both low and high carrier densities [99]. (f) Monolayer MoS₂ nanoribbon transistors, with (i) optical and SEM images showing the device dimension and (ii) key transistor properties affected by ribbon widths [100].

Fig.7 Synthetic 2D transistors. (a) Large-scale chemical assembly of graphene/MoS₂ heterostructures as arrayed FETs [103]. (b) Lateral VS₂−MoS₂−VS₂ heterostructures as synthetic transistors with low contact resistances [105]. (c) Synthetic arrays of vertical m-TMD/s-TMD heterostructures, with (i) showing the schematic structure, (ii) cross-section STEM image, (iii) optical image of the device arrays, and (iv) improved transfer characteristics [107]. (d) Short-channel bilayer WSe₂ transistors by direct chemical synthesis, with (i, ii) showing the schematic and optical images, respectively, of the device, (iii) SEM image of a short-channel device with L_ch~76 nm, and (iv) corresponding transfer characteristics [108].

Fig.8 Benchmarking 2D transistors. Three key parameters, namely channel length (L_ch, x-axis), contact resistance (R_C, y-axis) and field-effect mobility (μ_FE, z-axis), are extracted from previous works [47, 103, 105, 108–127]. The top right corner is the target being chased (stars: synthetic transistors; circles: nanofabricated transistors).

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