A high-speed true random number generator based on Ag/SiN<sub><i>x</i></sub>/n-Si memristor

doi:10.1007/s11467-023-1331-1

Front. Phys.

2024, Vol. 19

Issue (1) : 13202 https://doi.org/10.1007/s11467-023-1331-1

RESEARCH ARTICLE

A high-speed true random number generator based on Ag/SiN_x/n-Si memristor

Xiaobing Yan(

), Zixuan Zhang, Zhiyuan Guan, Ziliang Fang, Yinxing Zhang, Jianhui Zhao, Jiameng Sun, Xu Han, Jiangzhen Niu, Lulu Wang, Xiaotong Jia, Yiduo Shao, Zhen Zhao, Zhenqiang Guo, Bing Bai

Institute of Life Science and Green Development, Key Laboratory of Brain-Like Neuromorphic Devices and Systems of Hebei Province, College of Electron and Information Engineering, Hebei University, Baoding 071002, China

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Abstract

The intrinsic variability of memristor switching behavior can be used as a natural source of randomness, this variability is valuable for safe applications in hardware, such as the true random number generator (TRNG). However, the speed of TRNG is still be further improved. Here, we propose a reliable Ag/SiN_x/n-Si volatile memristor, which exhibits a typical threshold switching device with stable repeat ability and fast switching speed. This volatile-memristor-based TRNG is combined with nonlinear feedback shift register (NFSR) to form a new type of high-speed dual output TRNG. Interestingly, the bit generation rate reaches a high speed of 112 kb/s. In addition, this new TRNG passed all 15 National Institute of Standards and Technology (NIST) randomness tests without post-processing steps, proving its performance as a hardware security application. This work shows that the SiN_x-based volatile memristor can realize TRNG and has great potential in hardware network security.

Keywords volatile memristor true random number generator (TRNG) delay time threshold switching device

Corresponding Author(s): Xiaobing Yan

Issue Date: 13 September 2023

Cite this article:

Xiaobing Yan,Zixuan Zhang,Zhiyuan Guan, et al. A high-speed true random number generator based on Ag/SiN_x/n-Si memristor[J]. Front. Phys. , 2024, 19(1): 13202.

URL:

https://academic.hep.com.cn/fop/EN/10.1007/s11467-023-1331-1
https://academic.hep.com.cn/fop/EN/Y2024/V19/I1/13202

Fig.1 Characterization of the SiN_x film and ASS device. (a) TEM images of a cross-section of the SiN_x film grown on n-Si substrate. (b, c) The top-view images of the SiN_x film surface of TEM and AFM, respectively. (d) Schematic of the electrical measurement setup for characterizing the ASS structure. (e) 100 Consecutive DC switching cycles of the volatile memristor. (f) The resistance states distribution from 100 I–V cycles with the I_cc of 10^?5 A. (g) Cumulative distribution functions of threshold voltage V_th, V_h of the SiN_x/n-Si structure. (h, i) The distribution of the threshold/hold voltage with the I_cc of 10^?5 A, respectively.

Fig.2 The current response to the input voltage pulse of the devices. (a) A series of input pulses (blue line), consisting of variable width from 0.10 to 0.50 μs and the output voltage (red curve). (b) A series of input pulses (blue line), consisting of variable amplitude from 1.0 to 5.0 V, and the red line represents the corresponding output voltage. A higher input voltage leads to a larger output current. (c) The relaxation characteristic of using 3 V pulse and then using 1 V pulse, the time interval between the two pulses is 0 μs, 2.5 μs, 4.5 μs, 6.5 μs and the output voltage (red curve). (d) The retention characteristic of using 8 V pulse and then using a 1 V pulse, the time interval between the two pulses from 0 μs, 2.5 μs, 4.5 μs, 6.5 μs and the output voltage (red curve).

Fig.3 The effect of voltage and frequency on delay time. (a, b) Switching speed of the device. (c) Delay time distribution for different input pulse amplitudes (4 V, 4.5 V, 5 V, 5.5 V, 6 V). (d) Delay time distribution for different input pulse frequencies (60 kHz, 80 kHz, 100 kHz, 120 kHz, 140 kHz). (e) Conduct 100 cycle delay time statistics under the pulse with amplitude of 5 V and frequency of 1 MHz. (f) Relationship between average delay time and input voltage. (g) Relationship between average delay time and input frequency.

Fig.4 Implementation of the TRNG. (a) Circuit schematic diagram of TRNG. (b, c) Voltage test results of each test node. (d) Measured output results of two continuous periods of TRNG. (e) TRNG output demonstration process.

Tab.1 Comparison of this work with previously reported TRNG.

Test	$P$ -value	Pass rate	Min. pass rate	Pass/fail

1. Frequency	0.676097	81/85	80/85	Pass
2. Block frequency	0.701879	84/85	80/85	Pass
3. Cumulative sums	0.624107, 0.126842	82/85, 81/85	80/85	Pass
4. Runs	0.340461	84/85	80/85	Pass
5. Longest run	0.126842	84/85	80/85	Pass
6. Rank	0.947557	85/85	80/85	Pass
7. FFT	0.284375	83/85	80/85	Pass
8. Non overlapping template	?	12447/12580	11917/12580	Pass
9. Overlapping template	0.823278	81/85	80/85	Pass
10. Universal	0.999091	85/85	80/85	Pass
11. Approximate entropy	0.624107	83/85	80/85	Pass
12. Random excursions	?	413/416	388/416	Pass
13. Random excursions variant	?	928/936	874/936	Pass
14. Serial	0.572333, 0.448892	83/85, 83/85	80/85	Pass
15. Linear complexity	0.598138	83/85	80/85	Pass

Tab.2 NIST randomness test results.

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