Please wait a minute...
Frontiers of Computer Science

ISSN 2095-2228

ISSN 2095-2236(Online)

CN 10-1014/TP

邮发代号 80-970

2019 Impact Factor: 1.275

Frontiers of Computer Science  2014, Vol. 8 Issue (1): 131-144   https://doi.org/10.1007/s11704-013-3013-6
  本期目录
Adaptive in-page logging for flash-memory storage systems
Ke LU1,2, Peiquan JIN1,2(), Puyuan YANG1,2, Shouhong WAN1,2, Lihua YUE1,2
1. School of Computer Science and Technology, University of Science and Technology of China, Hefei 230026, China
2. Key Laboratory of Electromagnetic Space Information, Chinese Academy of Sciences, Hefei 230026, China
 全文: PDF(803 KB)  
Abstract

Flash memory is widely used in embedded devices and enterprise storage systems. Currently, flash-based storage devices usually use a flash translation layer (FTL) to cope with the special features of flash memory. Many methods for the design and implementation of the FTL have been proposed, such as BAST (block-associative sector translation), FAST (fully associative sector translation), and IPL (in-page logging), of which IPL has been demonstrated to have the best performance. However, IPL offers little consideration to reducing merge operations that consequently result in the degradation of the overall performance of flash-memory storage systems. We propose an improvement to IPL, called adaptive IPL (AIPL). The idea of adaptive IPL is to make the log region in a block resizable, therefore a hot block (i.e., a write-intensive block) will use a large log region so as to absorb more page updates and in turn reduce the merge operations, while a cold block, i.e., a block rarely written to, will use a small log region. This is realized by first detecting the update pattern of a block and then presenting an update-pattern-based algorithm to dynamically adjust the log region size of a newly allocated block. We conduct experiments on TPC-C traces and synthetic traces and compare the performance of AIPL with other competitors in terms of merge count, write count and elapsed time. The results demonstrate that compared with IPL, AIPL can reduce merge operations by 65% and write operations by 54% on average.

Key wordsflash memory    adaptive algorithm    IPL    update pattern
收稿日期: 2013-01-08      出版日期: 2014-02-01
Corresponding Author(s): Peiquan JIN   
 引用本文:   
. [J]. Frontiers of Computer Science, 2014, 8(1): 131-144.
Ke LU, Peiquan JIN, Puyuan YANG, Shouhong WAN, Lihua YUE. Adaptive in-page logging for flash-memory storage systems. Front. Comput. Sci., 2014, 8(1): 131-144.
 链接本文:  
https://academic.hep.com.cn/fcs/CN/10.1007/s11704-013-3013-6
https://academic.hep.com.cn/fcs/CN/Y2014/V8/I1/131
1 A LeVenthaL. Flash storage memory. Communications of the ACM, 2008, 51(7): 47−51
https://doi.org/10.1145/1364782.1364796
2 Z Liu, L Yue, P Wei, P Jin, X Xiang. An adaptive block-set based management for large-scale flash memory. In: Proceedings of the 2009 ACM Symposium on Applied Computing. 2009, 1621−1625
https://doi.org/10.1145/1529282.1529648
3 S W Lee, B Moon. Design of flash-based DBMS: an in-page logging approach. In: Proceedings of the 2007 ACM SIGMOD International Conference on Management of Data. 2007, 55−66
https://doi.org/10.1145/1247480.1247488
4 P Jin, Y Ou, T Härder, Z Li. AD-LRU: an efficient buffer replacement algorithm for flash-based databases. Data & Knowledge Engineering, 2012, 72: 83−102
https://doi.org/10.1016/j.datak.2011.09.007
5 T Cho, Y T Lee, E C Kim, J W Lee, S Choi, S Lee, D H Kim, W G Han, Y H Lim, J D Lee. A dual-mode nand flash memory: 1-GB multilevel and high-performance 512-MB single-level modes. IEEE Journal of Solid-State Circuits, 2001, 36(11): 1700−1706
https://doi.org/10.1109/4.962291
6 Understanding the flash translation layer (FTL) specification. Wishful Research Result AP-684, Intel Corporation, 1998
7 D Seo, D Shin. Recently-evicted-first buffer replacement policy for flash storage devices. IEEE Transactions on Consumer Electronics, 2008, 54(3): 1228−1235
https://doi.org/10.1109/TCE.2008.4637611
8 S Shaw, J Dyke. Pro Oracle Database 10g RAC on Linux: Installation, Administration, and Performance. Apress, 2006
9 Z Li, P Jin, X Su, K Cui, L Yue. CCF-LRU: a new buffer replacement algorithm for flash memory. IEEE Transactions on Consumer Electronics, 2009, 55(3): 1351−1359
https://doi.org/10.1109/TCE.2009.5277999
10 M Bjorling, P Bonnet, L Bouganim, B P Jónsson. MFLIP: Understanding the energy consumption of flash devices. IEEE Data Engineering Bulletin, 2010, 33(4): 48−54
11 A Gupta, Y Kim, B Urgaonkar. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. In: Proceedings of the 2009 International Conference on Architectural Support for Programming Languages and Operating System. 2009, 229−240
12 V Hudlet, D Schall. SSD!= SSD-an empirical study to identify common properties and type-specific behavior. In: Proceedings of the 14th Conference on GI-Conference on Database Systems for Business, Technology, and Web. 2011, 430−441
13 H Zhao, P Jin, P Yang, L Yue. BPCLC: an efficient write buffer management scheme for flash-based solid state disks. International Journal of Digital Contents and its Applications, 2010, 4(6): 123−133
14 Z Xu, R Li, C Z Xu. Cast: A page-level ftl with compact address mapping and parallel data blocks. In: Proceedings of the 31st IEEE International Performance Computing and Communications Conference. 2012, 142−151
15 D Ma, J Feng, G Li. LazyFTL: a page-level flash translation layer optimized for nand flash memory. In: Proceedings of the 2011 ACM SIG-MOD International Conference on Management of Data. 2011, 1−12
16 J Kim, J M Kim, S H Noh, S L Min, Y Cho. A space-efficient flash translation layer for compactflash systems. IEEE Transactions on Consumer Electronics, 2002, 48(2): 366−375
https://doi.org/10.1109/TCE.2002.1010143
17 J Boukhobza, P Olivier, S Rubini. Cach-ftl: A cache-aware configurable hybrid flash translation layer. In: Proceedings of the 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing. 2013, 94−101
18 I Shin. HA-SBAST: History-based flash translation layer for NAND flash memory. In: Proceedings of the 6th International Conference on Convergence and Hybrid Information Technology. 2012, 744−751
https://doi.org/10.1007/978-3-642-32645-5_93
19 S W Lee, D J Park, T S Chung, D H Lee, S Park, H J Song. A log buffer-based flash translation layer using fully-associative sector translation. ACM Transactions on Embedded Computing Systems, 2007, 6(3): 55−66
https://doi.org/10.1145/1275986.1275990
20 G J Na, S W Lee, B Moon. Dynamic in-page logging for flash-aware b-tree index. In: Proceedings of the 18th ACM Conference on Information and Knowledge Management. 2009, 1485−1488
21 P Jin, X Su, Z Li, L Yue. A flexible simulation environment for flashaware algorithms. In: Proceedings of the 18th ACM Conference on Information and Knowledge Management. 2009, 2093−2094
22 Samsung Electronics, K9XXG08UXA Datasheet. 2012
23 Y Ou, T Härder, P Jin. CFDC: a flash-aware buffer management algorithm for database systems. Lecture Notes in Computer Science, 2011, 6295 : 435−449
Viewed
Full text


Abstract

Cited

  Shared   
  Discussed