Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

doi:10.1007/s12200-013-0328-8

Front Optoelec

2013, Vol. 6

Issue (3) : 327-337 https://doi.org/10.1007/s12200-013-0328-8

RESEARCH ARTICLE

Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier

Bipin Kumar VERMA(

), Shyam Babu SINGH(

), Shyam AKASHE(

)

Department of Electronics and Communication Engineering, ITM University, Gwalior (M.P.) 474001, India

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Abstract

Multi-threshold complementary metal-oxide-semiconductor (MTCMOS) is often used to reduce the leakage current in idle circuit. Ground bounce noise produced during a transition mode (sleep-to-active) is an important challenge in MTCMOS. In this paper, various noise-aware combinational MTCMOS circuit was used to evaluate the ground bounce noise. An intermediate mode was applied in the sleep-to-active mode transition to reduce the charge stored on virtual lines to real ground. The dependence of ground bounce noise on voltage, transistor size and temperature was investigated with different MTCMOS circuit technique. The peak amplitude of ground bounce noise was reduced up to 78.82%. The leakage current of the circuit was decreased up to 99.73% and the active power of the circuit was reduced up to 62.32%. Simulation of multiplier with different MTCMOS circuit techniques was performed on 45 nm CMOS technology.

Keywords multi-threshold complementary metal-oxide-semiconductor (MTCMOS) mode transition ground bounce noise sleep transistor

Corresponding Author(s): VERMA Bipin Kumar,Email:bipinverma05@gmail.com; SINGH Shyam Babu,Email:itm.shyam@gmail.com; AKASHE Shyam,Email:shyam.akashe@yahoo.com

Issue Date: 05 September 2013

Cite this article:

Shyam AKASHE,Bipin Kumar VERMA,Shyam Babu SINGH. Ground bounce noise reduction aware combinational multi threshold CMOS circuits for nanoscale CMOS multiplier[J]. Front Optoelec, 2013, 6(3): 327-337.

URL:

https://academic.hep.com.cn/foe/EN/10.1007/s12200-013-0328-8
https://academic.hep.com.cn/foe/EN/Y2013/V6/I3/327

Fig.1 Power and ground bounce noise generated in conventional MTCMOS technique on multiplier circuit

Fig.2 Basic operation of multiplier

Fig.3 Design of 4 × 4 bit-array multiplier (HA=half adder, FA=full adder)

Fig.4 Tri-mode MTCMOS technique [].

Fig.5 Dual-switch MTCMOS technique []. High-TH sleep transistors are represented by thick channel length. 0 V<MIN<DD

Fig.6 Tri-transistor-controlled MTCMOS circuit. (a) TTH; (b) TTL []. High-TH sleep transistors are represented by thick channel length. 0 V<MIN<DD

Fig.7 DIP-40 package pin ground bounce noise model

Tab.1 Effect of voltage scaling on ground bounce noise (unit: mV)

Fig.8 Percentage ground bounces noise reduction provided by different MTCMOS circuit techniques as compared to conventional circuit.

Fig.9 Waveform showing ground bounce noise at real ground (0.9 V and / = 2.67 nm). (a) Conventional design; (b) tri-mode design; (c) dual-switch design; (d) TTH; (e) TTL

Fig.10 Waveform of virtual ground line voltage of TTH circuit during transitions from sleep-to-active mode through doze mode. The duration of doze mode is 87.41 ns. (a) Virtual ground line voltage with small doze (dozer = 2.67 nm); (b) virtual ground line voltage with larger doze (dozer = 15 nm)

Tab.2 Relaxation time for different circuits (unit: ns)

Fig.11 Waveform of real ground voltage of TTH circuit during transitions from the sleep-to-active mode through doze mode. The duration of doze mode is 87.41 ns. (a) Ground bounce noise on real ground with smaller doze (dozer = 2.67 nm). (b) ground bounce noise on real ground with larger doze (dozer = 15 nm)

Tab.3 Effect of transistor size on ground bounce noise (unit: mV)

Fig.12 Peak amplitude of ground bounces noise for tri-mode, dual-switch, TTH and TTL at different temperatures

Tab.4 Leakage current consumption (unit: nA)

Fig.13 Percentage leakage current reduction provided by different MTCMOS circuit techniques as compared to conventional circuit (sleep mode)

Tab.5 Active power consumption (unit: mW)

Tab.6 Performance comparison of different MTCMOS circuits

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