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Frontiers of Computer Science

ISSN 2095-2228

ISSN 2095-2236(Online)

CN 10-1014/TP

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2018 Impact Factor: 1.129

Front. Comput. Sci.    2009, Vol. 3 Issue (3) : 290-301    https://doi.org/10.1007/s11704-009-0028-0
Research articles
Four styles of parallel and net programming
Zhiwei XU 1, Li ZHA 1, Yongqiang HE 2, Wei LIN 2,
1.Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China; 2.Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;Graduate School of the Chinese Academy of Sciences, Beijing 100039, China;
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Abstract This paper reviews the programming landscape for parallel and network computing systems, focusing on four styles of concurrent programming models, and example languages/libraries. The four styles correspond to four scales of the targeted systems. At the smallest coprocessor scale, Single Instruction Multiple Thread (SIMT) and Compute Unified Device Architecture (CUDA) are considered. Transactional memory is discussed at the multicore or process scale. The MapReduce style is examined at the datacenter scale. At the Internet scale, Grid Service Markup Language (GSML) is reviewed, which intends to integrate resources distributed across multiple datacenters. The four styles are concerned with and emphasize different issues, which are needed by systems at different scales. This paper discusses issues related to efficiency, ease of use, and expressiveness.
Keywords concurrent programming      CUDA      SIMT      transactional memory      MapReduce      GSML      
Issue Date: 05 September 2009
 Cite this article:   
Zhiwei XU,Li ZHA,Yongqiang HE, et al. Four styles of parallel and net programming[J]. Front. Comput. Sci., 2009, 3(3): 290-301.
 URL:  
https://academic.hep.com.cn/fcs/EN/10.1007/s11704-009-0028-0
https://academic.hep.com.cn/fcs/EN/Y2009/V3/I3/290
Bryant R. Data-intensivesupercomputing: the case for DISC. TechnicalReport CMU-CS-07-128, Carnegie Mellon University, 2007
Chaiken R, Jenkins B, Larson P, et al. SCOPE: easy and efficient parallel processingof massive data sets. In: InternationalConference of Very Large Data Bases (VLDB). VLDB Endowment, 2008, 1265―1276
Cooper B, Ramakrishnan R, et al. PNUTS: Yahoo!’shosted data serving platform. In: InternationalConference of Very Large Data Bases (VLDB). VLDB Endowment, 2008, 1277―1278
Dean J, Ghemawat S. MapReduce: simplified dataprocessing on large clusters. In: Proceedingsof the 6th Symposium on Operating Systems Design and Implementation.USENIX Association, 2004, 137―150
Garland M, Grand S, Nickolls J, et al. Parallel computing experiences with CUDA. IEEE Micro, 2008, 28(4): 13―27

doi: 10.1109/MM.2008.57
Guerraoui R, Herlihy M, Pochon B. Polymorphic contention management. In: Proceedings of the 19th International Symposium on DistributedComputing. New York: Springer Verlag, 2005, 303―323
Harris T, Fraser T. Language support for lightweighttransactions. In: Proceedings of the 8thAnnual ACM SIGPLAN Conference on Object-oriented Programming, Systems,Languages, and Applications. NewYork: ACM Press, 2003, 388―402
Harris T, Marlow S, Peyton-Jones S, et al. Composable memory transactions. In: Proceedings of the 10th ACM SIGPLAN Symposium on Principles andPractice of Parallel Programming. New York: ACM Press, 2005, 48―60
Herlihy M, Eliot J, Moss B. Transactional memory: architectural support for lock-freedata structures. In: Proceedings of the20th Annual International Symposium on Computer Architecture. New York: ACM Press, 1993, 289―300
Herlihy M, Luchangco V, Moir M, Scherer III W N. Software transactional memory for dynamic-sized data structures. In: Proceedings of the 22nd Annual Symposium onPrinciples of Distributed Computing. New York: ACM Press, 2003, 92―101
Herlihy M, Nir Shavit. The art of multiprocessorprogramming. Morgan Kaufmann, 2008
Hwang K. Xu Z. Scalable parallel computing:technology, architecture, programming. McGraw-Hill Science/Engineering/Math, 1998
Khronos Group. TheOpenCL specification, version 1.0. 12/08/2008
Larus J, Kozyrakis C. Transactional memory. New York: Communication of the ACM, 2008, 51(7): 80―88

doi: 10.1145/1364782.1364800
Larus R, Rajwar R. Transactional memory. Morgan & Claypool, 2006
Liu X, Radenac Y, Ban atre J, et al. A chemical interpretation of GSML programs. In: 7th International Conference on Grid and CooperativeComputing(GCC2008). 2008, 459―466
Minh C, Trautmann M, Chung J, et al. An effective hybrid transactional memory systemwith strong isolation guarantees. In: Proceedingsof the 34th International Symposium on Computer Architecture. New York: ACM Press, 2007, 69―80
NVIDIA. Corp. NVIDIACUDA programming guide, version 2.0. 06/07/2008
Owens J, Luebke D, et al. A survey of general-purposecomputation on graphics hardware. ComputerGraphics Forum. 2007, 26(1): 80―113

doi: 10.1111/j.1467-8659.2007.01012.x
Patterson D. Thedata center is the computer. New York: Communication of the ACM, 2008, 51(1): 105―105

doi: 10.1145/1327452.1327491
Ryoo S, Rodrigues C, Baghsorkhi S, et al. Optimization principles and application performanceevaluation of a multithreaded GPU using CUDA. In: Proceedings of the 13th Symposium on Principles and Practiceof Parallel Programming. New York: ACMPress, 2008, 73―82
Saha B, Adl-Tabatabai R, Jacobson Q. Architectural support for software transactional memory. In: Proceedings of the 39th International Symposiumon Microarchitecture. 2006, 185―196
Scherer III W N, Scott M L. Advanced contention managementfor dynamic software transactional memory. In: Proceedings of the 24th Annual ACM SIGACT-SIGOPS Symposium onPrinciples of Distributed Computing. New York: ACM Press, 2005, 240―248
Shavit N, Touitou D. Software transactional memory. In: Proceedings of the 14th ACM Symposium on Principlesof Distributed Computing. NewYork: ACM Press, 1995, 204―213
Shu C, Yu H, Liu H. Beap: an end-user agile programming paradigm for businessapplications. Journal of Computer Scienceand Technology, 2006, 21(4): 609―619

doi: 10.1007/s11390-006-0609-4
Tarditi D, Puri S, et al. Accelerator: usingdata parallelism to program GPUs for general-purpose uses. In: Proceedings of the 12th International Conferenceon Architectural Support for Programming Languages and Operating Systems. 2006, 325―335
Volkov V, Demmel J. Benchmarking GPUs to tunedense linear algebra. In: Proceedings ofConference on Supercomputing. IEEE Press, 2008
Zaharia M, Konwinski A, Joseph A, et al. Improving MapReduce performance in heterogeneousenvironments. In: 8th Symposium on OperatingSystems Design and Implementation. USENIX Association, 2008
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