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Frontiers of Computer Science

ISSN 2095-2228

ISSN 2095-2236(Online)

CN 10-1014/TP

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2018 Impact Factor: 1.129

Front. Comput. Sci.    2013, Vol. 7 Issue (5) : 650-672    https://doi.org/10.1007/s11704-013-3094-6
RESEARCH ARTICLE
Scenario-based verification in presence of variability using a synchronous approach
Jean-Vivien MILLO1(), Frédéric MALLET2, Anthony COADOU3, S RAMESH3
1. INRIA Sophia-Antipolis, Aoste team (INRIA/I3S/CNRS/UNS), Sophia-Antipolis 06560, France
2. University of Nice Sophia Antipolis, Sophia-Antipolis 06900, France
3. Global General Motors R&D, India Science Lab, GM Technical Center India, Bangalore 560066, India
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Abstract

This paper presents a new model of scenarios, dedicated to the specification and verification of system behaviours in the context of software product lines (SPL). We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components. We point out the benefits of synchronous languages and models to bridge the gap between both worlds.

Keywords Esterel      UML MARTE      scenario      verification      feature interaction      variability     
Corresponding Author(s): Jean-Vivien MILLO   
Issue Date: 01 October 2013
 Cite this article:   
Jean-Vivien MILLO,Frédéric MALLET,Anthony COADOU, et al. Scenario-based verification in presence of variability using a synchronous approach[J]. Front. Comput. Sci., 2013, 7(5): 650-672.
 URL:  
https://academic.hep.com.cn/fcs/EN/10.1007/s11704-013-3094-6
https://academic.hep.com.cn/fcs/EN/Y2013/V7/I5/650
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