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Frontiers of Computer Science

ISSN 2095-2228

ISSN 2095-2236(Online)

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Front. Comput. Sci.    2025, Vol. 19 Issue (1) : 191103    https://doi.org/10.1007/s11704-023-3239-x
Architecture
RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb
Libo HUANG, Jing ZHANG, Ling YANG, Sheng MA, Yongwen WANG, Yuanhu CHENG()
College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China
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Abstract

The rapid development of ISAs has brought the issue of software compatibility to the forefront in the embedded field. To address this challenge, one of the promising solutions is the adoption of a multiple-ISA processor that supports multiple different ISAs. However, due to constraints in cost and performance, the architecture of a multiple-ISA processor must be carefully optimized to meet the specific requirements of embedded systems. By exploring the RISC-V and ARM Thumb ISAs, this paper proposes RVAM16, which is an optimized multiple-ISA processor microarchitecture for embedded devices based on hardware binary translation technique. The results show that, when running non-native ARM Thumb programs, RVAM16 achieves a significant speedup of over 2.73× with less area and energy consumption compared to using hardware binary translation alone, reaching more than 70% of the performance of native RISC-V programs.
Keywords multiple-ISA processor      architecture      binary translation      RISC-V      embedded     
Corresponding Author(s): Yuanhu CHENG   
Just Accepted Date: 31 October 2023   Issue Date: 18 March 2024
 Cite this article:   
Libo HUANG,Jing ZHANG,Ling YANG, et al. RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb[J]. Front. Comput. Sci., 2025, 19(1): 191103.
 URL:  
https://academic.hep.com.cn/fcs/EN/10.1007/s11704-023-3239-x
https://academic.hep.com.cn/fcs/EN/Y2025/V19/I1/191103
Technique Pros Cons
Multi-core Independent performance for different ISAs High hardware cost
Multi-decoder Same performance for different ISAs Complex pipeline
HBT Low hardware cost Lower performance for non-native ISA
Tab.1  The features of different multiple-ISA processor techniques
Fig.1  Multiple-ISA processor microarchitecture based on binary translation
Fig.2  Microarchitecture of RVAM16 processor core
ARM Thumb registers (encoding) RISC-V registers (encoding)
R0−R7 (000−111) R16−R23 (10000−10111)
R8−R12 (1000−1100) R24−R28 (11000−11100)
SP (1101) R29 (11101)
LR (1110) R30 (11110)
PC (1111) PC/R31 (11111)
Tab.2  Register mapping from ARM Thumb to RISC-V
Fig.3  
Fig.4  Architecture of hardware binary translator in RVAM16
Fig.5  Structure of RVAM16 ALU
Instruction category Instruction Translation ratio
Without optimization With optimization
Move MOV Rd, Rm 1 1
MOV PC, Rm 1 1
MOV Rd, PC 2 2
MOVS Rd, Rm 4 1
MOVS Rd, imm 4 1
Add ADD Rd, SP, imm 1 1
ADD Rd, Rd, Rm 1 1
ADD Rd, Rd, PC 2 2
ADD PC, PC, Rm 3 3
ADR Rd, <label> 3 3
ADDS Rd, Rd, imm 8 1
ADDS Rd, Rm, Rn 9 1
ADDS Rd, Rm, imm 9 1
ADCS Rd, Rd, Rm 16 1
Subtract SUB SP, SP, imm 2 2
SUBS Rd, Rm, Rn 17 1
SBCS Rd, Rd, Rm 17 1
RSBS Rd, Rm, 0 17 1
SUBS Rd, Rm, imm 18 1
SUBS Rd, Rd, imm 18 1
Multiply MUL Rd, Rm, Rd 4 1
Compare CMN Rm, imm 8 1
CMP Rm, Rn 16 1
CMP Rn, imm 17 2
Logic LOPaRd, Rd, Rm 4 1
BICS Rd, Rd, Rm 5 2
Shift SOPbRd, Rd, Rm 8 1
SOPbRd, Rm, imm 9 1
RORS Rd, Rd, Rm 10 6
Load LDRIc Rd, Rm, imm 1 1
LDRRd Rd, Rm, Rn 2 2
LDR Rd, <label> 3 3
LDM Rm, registers ne ne
Store STRXf Rd, Rm, imm 1 1
STRXf Rd, Rm, Rn 2 2
STM Rm, registers ne ne
Stack POP registers ne ne
PUSH registers ne ne
Branch BXXg 1 1
BGT 4 1
BLE 4 1
Extend EOP Rd, Rm 2 2
Reverse REVSH Rd, Rm 5 5
REV Rd, Rm 11 11
REV16 Rd, Rm 11 11
Tab.3  Instruction translation ratio in ARMv6-M without and with optimization
Fig.6  Performance of running Dhrystone and CoreMark benchmarks
Fig.7  Performance of running Embench benchmark suite
Real case Kernel program Execution time
RISC-V Thumb
Communication program UART 1.10 1.23
Temperature control system Sensor access 1.19 1.38
Flash control system Flash access 1.50 1.53
Tab.4  Relative execution time of RVAM16 running real applications
Name Technique Native ISA Non-native ISA Slowdown
Software QEMU [6] DBT X86/ARM/Other RISC-V 7.07× [12]
QEMU DBT RISC-V X86 more than 3.50× [23]
RV8 [9] DBT X86 RISC-V 2.60×
Lupori et al. [12] SBT X86/ARM RISC-V 1.12×/1.35×
Hardware Capella et al. [18] HBT + extended MIPS MIPS X86/ARM/PowerPC about 1.57×/2.03×/2.22×
HBT HBT RISC-V ARM 4.89×
RVAM16 HBT + hardware optimization RISC-V ARM 1.40×
Tab.5  Compareison between state-of-the-art software binary translation system and HBT-based multiple-ISA processors
Core Area (μm2) Benchmark (Target ISA) Power (mW) Relative energy
Static Dynamic Total
RVAM16 24269.28 Dhrystone (RISC-V) 1.69 1.51 3.20 0.84
CoreMark (RISC-V) 1.69 1.59 3.28 0.90
Dhrystone (ARM Thumb) 1.71 1.70 3.41 1.25
CoreMark (ARM Thumb) 1.70 1.78 3.48 1.26
RISC-V + HBT 26658.41 Dhrystone (RISC-V) 1.86 1.48 3.34 0.87
CoreMark (RISC-V) 1.86 1.55 3.41 0.94
Dhrystone (ARM Thumb) 1.87 1.77 3.64 3.65
CoreMark (ARM Thumb) 1.87 1.71 3.58 5.59
Base RISC-V Core 20757.91 Dhrystone (RISC-V) 1.37 1.42 2.79 0.73
CoreMark (RISC-V) 1.36 1.53 2.89 0.79
Ibex 32802.67 Dhrystone (RISC-V) 2.29 2.70 4.99 0.93
CoreMark (RISC-V) 2.29 3.26 5.55 1.04
Cortex-M0 26264.45 Dhrystone (ARM Thumb) 2.41 1.80 4.21 1.00
CoreMark (ARM Thumb) 2.41 1.85 4.26 1.00
Tab.6  Area, power and energy consumption of processors at 100 MHz and 0.81 V
Fig.8  Area and power distribution of RVAM16
  
  
  
  
  
  
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