Finite element analysis of temperature distribution of polycrystalline silicon thin film transistors under self-heating stress

doi:10.1007/s11460-009-0023-0

Front Elect Electr Eng Chin

2009, Vol. 4

Issue (2) : 227-233 https://doi.org/10.1007/s11460-009-0023-0

RESEARCH ARTICLE

Finite element analysis of temperature distribution of polycrystalline silicon thin film transistors under self-heating stress

Huaisheng WANG, Mingxiang WANG(

), Zhenyu YANG

Department of Microelectronics, Soochow University, Suzhou 215021, China

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Abstract

The temperature distribution of typical n-type polycrystalline silicon thin film transistors under self-heating (SH) stress is studied by finite element analysis. From both steady-state and transient thermal simulation, the influence of device power density, substrate material, and channel width on device temperature distribution is analyzed. This study is helpful to understand the mechanism of SH degradation, and to effectively alleviate the SH effect in device operation.

Keywords finite element analysis (FEA) temperature distribution thin film transistors self-heating steady-state transient state

Corresponding Author(s): WANG Mingxiang,Email:Mingxiang_wang@suda.edu.cn

Issue Date: 05 June 2009

Cite this article:

Huaisheng WANG,Mingxiang WANG,Zhenyu YANG. Finite element analysis of temperature distribution of polycrystalline silicon thin film transistors under self-heating stress[J]. Front Elect Electr Eng Chin, 2009, 4(2): 227-233.

URL:

https://academic.hep.com.cn/fee/EN/10.1007/s11460-009-0023-0
https://academic.hep.com.cn/fee/EN/Y2009/V4/I2/227

Fig.1 Schematic illustration of cross section of TFT

Fig.2 Transfer characteristic degradation of n-channel MILC TFT under SH stress

Fig.3 Single device finite element model used for TFT thermal analysis

Tab.1 Electrical stress conditions simulated in thermal analysis models with different / and substrate types

Tab.2 Table 2 Thermal parameters of different materials used in simulation

Fig.4 Channel temperature distribution simulated in /=10 μm/6 μm TFT model on Si substrate with stress power=27.9 mW

Fig.5 Channel temperature distribution crossing peak temperature point in linear and saturation regions simulated in /=10 μm/6 μm TFT model on Si substrate. (a) Along channel length direction; (b) along channel width direction; (c) along thickness direction from the bottom SiO to device surface

Fig.6 Fig. 6 Channel temperature distribution crossing peak temperature point simulated in TFT models on Si substrate with different /. (a) Along channel length direction; (b) along the relative position in channel width

Fig.7 Channel peak temperature dependent on stress power density simulated in TFT models on Si substrate with different /

Fig.8 Channel temperature distribution crossing peak temperature point simulated in /=10 μm/6 μm TFT model on glass substrate. (a) Along channel length direction; (b) along channel width direction; (c) along thickness direction from the bottom SiO to device surface

Fig.9 Transient rising and falling temperature curves simulated in TFT model with /=200 μm/6 μm on Si substrate

Fig.10 Falling time constant dependent on from TFT models with different / on Si or glass substrate

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