System-level Pareto frontiers for on-chip thermoelectric coolers

doi:10.1007/s11708-018-0540-8

Front. Energy

2018, Vol. 12

Issue (1) : 109-120 https://doi.org/10.1007/s11708-018-0540-8

RESEARCH ARTICLE

System-level Pareto frontiers for on-chip thermoelectric coolers

Sevket U. YURUKER¹, Michael C. FISH¹, Zhi YANG¹, Nicholas BALDASARO², Philip BARLETTA³, Avram BAR-COHEN¹(

), Bao YANG¹(

)

¹. Department of Mechanical Engineering, University of Maryland, College Park, MD 20742, USA
². Research Triangle Institute, Research Triangle Park, NC 27709, USA
³. Micross Components, Research Triangle Park, NC 27709, USA

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Abstract

The continuous rise in heat dissipation of integrated circuits necessitates advanced thermal solutions to ensure system reliability and efficiency. Thermoelectric coolers are among the most promising techniques for dealing with localized on-chip hot spots. This study focuses on establishing a holistic optimization methodology for such thermoelectric coolers, in which a thermoelectric element’s thickness and the electrical current are optimized to minimize source temperature with respect to ambient, when the thermal and electrical parasitic effects are considered. It is found that when element thickness and electrical current are optimized for a given system architecture, a “heat flux vs. temperature difference” Pareto frontier curve is obtained, indicating that there is an optimum thickness and a corresponding optimum current that maximize the achievable temperature reduction while removing a particular heat flux. This methodology also provides the possible system level ΔT’s that can be achieved for a range of heat fluxes, defining the upper limits of thermoelectric cooling for that architecture. In this study, use was made of an extensive analytical model, which was verified using commercially available finite element analysis software. Through the optimization process, 3 pairs of master curves were generated, which were then used to compose the Pareto frontier for any given system architecture. Finally, a case study was performed to provide an in-depth demonstration of the optimization procedure for an example application.

Keywords thermoelectric cooling thermal management optimization high flux electronics

Corresponding Author(s): Avram BAR-COHEN,Bao YANG

Just Accepted Date: 03 January 2018 Online First Date: 08 February 2018 Issue Date: 08 March 2018

Cite this article:

Sevket U. YURUKER,Michael C. FISH,Zhi YANG, et al. System-level Pareto frontiers for on-chip thermoelectric coolers[J]. Front. Energy, 2018, 12(1): 109-120.

URL:

https://academic.hep.com.cn/fie/EN/10.1007/s11708-018-0540-8
https://academic.hep.com.cn/fie/EN/Y2018/V12/I1/109

Fig.1 Schematic of (a) element level temperature difference ΔT_e; (b) system level temperature difference ΔT_sys in a typical thermoelectric cooling system architecture

Fig.2 (a) Heat pumped vs system level ΔT_sys curves for different TE thicknesses and (b) the corresponding frontier curves for a given system level architecture that sums up to a structural resistance R_str = 20 K/W, obtained using the revised TE equations (Eqs. (8)–(11))

Fig.3 Discrepancy between element level ΔT_e and system level ΔT_sys due to structural thermal parasitics for an example module with 100 µm thick TE element

Fig.4 Percentage breakdown of electrical resistances for (a) thin film TEC and (b) bulk TEC, when the Cu trace thickness is 50 µm and the electrical contact resistance is ECR= 1 × 10⁻¹⁰ W·m², which reflect today’s capabilities [7,17]

Fig.5 Effect of electrical contact resistance on achievable heat fluxes when Δt = 0 (For comparison with the following sections of the paper, the corresponding “areal” resistance for the R_str = 0.1 K/W curve is R_str,areal = 1.23 × 10⁻⁴ cm²·K/W)

Fig.6 Cu trace thickness optimization

Fig.7 (a) Unit cell based, numerical model geometry; (b) dimensions and material properties of the system; (c) thermal resistance network of the system

Fig.8 Analytical model results comparison with numerical results obtained via ANSYS

Fig.9 Analytical model results comparison with experimental results obtained by Bulman et al. [7]

Fig.10 Master curves of Q-ΔT for various structural resistances at (a) T_sink = 300 K, and (b) T_sink = 400 K

Fig.11 Master curves of optimized TE element thicknesses for various structural resistances at (a) T_sink = 300 K, and (b) T_sink = 400 K

Fig.12 Master curves of optimal current densities for various structural resistances at (a) T_sink = 300 K, and (b) T_sink = 400 K

Tab.1 Dimensions and assumed thermal conductivities for the case study model

Fig.13 The 3D model of the system built in Ansys-Workbench

Fig.14 (a) Pareto frontier; (b) optimal values of the variables obtained using three different methods; the master curves, analytical optimization and simulation

A	Area/m²
COP	Coefficient of performance
HTC	Heat transfer coefficient/(W·m^–2·K^–1)
I	Electrical current/A
k	Thermal conductivity of TE element/(W·m^–1·K^–1)
K	Conductance of the TE element/(W·K^–1)
L	Thickness of the TE element/m
N	Number of elements within the thermoelectric module
Q	Net heat pumped at the specified junction/W
Q_s	Heat flow from the source per TE element/W
$q ″$	Heat flux/(W·cm^–2)
R_source	Sum of source side structural resistances per TE element/(K·W ^–1)
R_sink	Sum of sink side structural resistances per TE element/(K·W^–1)
R_str,areal	Area based version of the structural resistance/(cm²·K·W^–1)
R_TE	Electrical resistance of TE element/W
S	Seebeck coefficient per TE element/(V·K^–1)
T	Temperature/K
TE	Thermoelectric element
TEC	Thermoelectric cooler
T_source	Source temperature/K
T_sink	Sink (fluid) temperature/K
Greek symbols
$Δ$	Difference in temperature/K
$γ$	Ratio of sink side resistance to total structural resistance
$ρ$	Electrical resistivity of TE element/(W·m)
$ρ ECR$	Electrical contact resistivity/(W·m²)
Subscripts
c	Cold junction of the TE element
e	Element-level
ECR	Electrical contact resistance
eff	Effective
elec	Electrical
h	Hot junction of the TE element
opt	Optimum value for the variable
s	Source
spr	Spreading
str	Structural
sys	System-level
TE	Thermoelectric element
Trace	Electrical resistance of the Cu trace

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