Emerging trend for LED wafer level packaging

doi:10.1007/s12200-012-0259-9

Front Optoelec

2012, Vol. 5

Issue (2) : 119-126 https://doi.org/10.1007/s12200-012-0259-9

REVIEW ARTICLE

Emerging trend for LED wafer level packaging

S. W. Ricky LEE^1,2(

), Rong ZHANG¹, K. CHEN¹, Jeffery C. C. LO¹

1. Center for Advanced Microsystems Packaging, The Hong Kong University of Science & Technology (HKUST), Hong Kong, China; 2. HKUST LED-FPD Technology R&D Center at Foshan, Guangdong 528200, China

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Abstract

Currently most light emitting diode (LED) components are made with individual chip packaging technology. The main manufacturing processes follow conventional chip-based IC packaging. In the past several years, there has been an uprising trend in the IC industry to migrate from chip-based packaging to wafer level packaging (WLP). Therefore, there is a need for LEDs to catch up. This paper introduces advanced LED WLP technologies. The contents cover key enabling processes such as preparation of silicon sub-mount wafer, implementation of interconnection, deposition of phosphor, wafer level encapsulation, and their integration. The emphasis is placed on how to achieve high throughput, low cost manufacturing through WLP.

Keywords light emitting diode (LED) wafer level packaging (WLP)

Corresponding Author(s): LEE S. W. Ricky,Email:leesw@fsldctr.org

Issue Date: 05 June 2012

Cite this article:

S. W. Ricky LEE,Rong ZHANG,K. CHEN, et al. Emerging trend for LED wafer level packaging[J]. Front Optoelec, 2012, 5(2): 119-126.

URL:

https://academic.hep.com.cn/foe/EN/10.1007/s12200-012-0259-9
https://academic.hep.com.cn/foe/EN/Y2012/V5/I2/119

Fig.1 Some common types of LEDs and their relevant packaging process flows (does not include the flip chip version of LEDs)

Fig.2 Industrial survey projects a high CAGR for WLP []

Fig.3 Wafer level phosphor printing for LED color tuning []

Fig.4 Wafer level dispensing for LED encapsulation []

Fig.5 LED WLP process flow with integrated phosphor printing for color tuning and moldless dispensing for encapsulation []

Fig.6 LED arrays fabricated with integrated WLP processes [].
(a) LED arrays after WLP; (b) on-wafer illumination test

Fig.7 Singulated component of LED WLP []

Fig.8 Current industrial practice of LED WLP
(http://www.tsmc.com/english/lighting/index.htm)

Fig.9 LED WLP on a silicon sub-mount with cavities by tMt
(http://www.tmt-mems.com/solutions.html)

Fig.10 LED WLP on a silicon sub-mount with cavities by Shinko
(http://www.shinko.co.jp/english/corporate/outline.html)

Fig.11 Schematic diagram of process flow for a silicon sub-mount with cavities and TSVs []: (a) via and cavity etching; (b) via filling; (c) KOH and BOE etching to expose copper pillars; (d) solder plating; (e) reflow and RDL patterning; (f) LED chip mounting; (g)?phosphor printing

Fig.12 Prototype of a silicon sub-mount with cavities and TSVs suitable for LED flip chip mounting []: placed solder (a) on copper pillars before reflow; (b) after reflow, and (c) cross-section of substrate

Fig.13 Prototype of LED WLP with LED flip chips mounted on a silicon sub-mount with cavities and TSVs, and printed with yellow phosphor []: LED chip (a) mounted in cavity; (b) covered by phosphor powder; (c) cross-section of package

Fig.14 Illumination of LED WLP prototype with LED flip chips mounted on silicon sub-mount with cavities and TSVs []: LED package (a) without phosphor printing; (b) with phosphor printing

Fig.15 Proposal for full LED WLP

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