High performance of low voltage controlled ring oscillator with reverse body bias technology

doi:10.1007/s12200-013-0348-4

Front Optoelec

2013, Vol. 6

Issue (3) : 338-345 https://doi.org/10.1007/s12200-013-0348-4

RESEARCH ARTICLE

High performance of low voltage controlled ring oscillator with reverse body bias technology

Akansha SHRIVASTAVA(

), Anshul SAXENA, Shyam AKASHE

Electronics and Communication Department, ITM University, Gwalior 474001, India

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Abstract

In complementary metal oxide semiconductor (CMOS) nanoscale technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for critical communication systems with high oscillation frequency. An ideal approach has been presented with substrate biasing technique for reduction of power consumption. The simulation have been completed using cadence virtuoso 45 nm standard CMOS technology at room temperature 27°C with supply voltage V_dd = 0.7 V. The simulation results suggest that voltage controlled ring oscillator has characterized with efficient low power voltage controlled oscillator (VCO) in term of minimum leakage power (1.23 nW) and maximum oscillation frequency (4.76 GHz) with joint positive channel metal oxide semiconductor and negative channel metal oxide semiconductor (PMOS and NMOS) reverse substrate bias technique. PMOS, NMOS and joint reverse body bias techniques have been compared in the presented work.

Keywords voltage controlled oscillator (VCO) leakage power active power oscillation frequency efficiency cadence tool

Corresponding Author(s): SHRIVASTAVA Akansha,Email:erakansha.mp@gmail.com

Issue Date: 05 September 2013

Cite this article:

Akansha SHRIVASTAVA,Anshul SAXENA,Shyam AKASHE. High performance of low voltage controlled ring oscillator with reverse body bias technology[J]. Front Optoelec, 2013, 6(3): 338-345.

URL:

https://academic.hep.com.cn/foe/EN/10.1007/s12200-013-0348-4
https://academic.hep.com.cn/foe/EN/Y2013/V6/I3/338

Fig.1 Five stage VCO ring oscillator

Fig.2 Waveform of VCO ring oscillator.

Fig.3 Inverter schematic diagram using PMOS and NMOS, where varies from 0.7 to1.8 V

Fig.4 Ring oscillator schematic diagram using PMOS and NMOS, with NMOS reverse substrate bias, where varies from 0.7 to 1.8 V

Fig.5 Ring oscillator schematic diagram using PMOS and NMOS, with PMOS reverse substrate bias, where varies from 0.7 to 1.8 V

Fig.6 Ring oscillator schematic diagram using PMOS and NMOS, with joint PMOS and NMOS reverse substrate bias, where varies from 0.7 to 1.8 V

Tab.1 Oscillation frequency of five stages VCO ring oscillator.

Tab.2 Active power of ring oscillator with NMOS, PMOS, joint PMOS & NMOS reverse substrate bias techniques

Tab.3 Leakage power of ring oscillator with NMOS, PMOS joint PMOS and NMOS reverse subtract bias techniques

Fig.7 parameter of Smith chart

Fig.8 parameter of Smith chart

Fig.9 Efficiency of Voltage controlled oscillator with joint reverse substrate bias

Tab.4 Compression of joint PMOS and NMOS reverse body bias between pervious published paper and presented paper

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